The present invention relates to a method of manufacturing an SOI (Silicon On Insulator) semiconductor element for obtaining a high-speed operation and, more particularly, to a method of manufacturing an SOI MOS field-effect semiconductor element.
A conventional SOI semiconductor element is shown in FIG. 2. FIG. 2 is a longitudinal sectional view of an SOI MOS field-effect semiconductor element. Reference numeral 1 denotes a silicon substrate; 2, an SiO.sub.2 buried oxide film for electrically insulating a silicon active layer 3 of a first conductivity type (e.g., p-type) from the silicon substrate 1; and 4, an SiO.sub.2 gate oxide film serving as a gate insulator. Reference numeral 5 denotes a source region of a second conductivity type (e.g., n-type); 6, a drain region of the second conductivity type (e.g., n-type); 7, a gate electrode; 8, an insulator for electrically insulating interconnections from each other; 9, a source electrode; and 10, a drain electrode.
An SOI semiconductor element of this type is arranged as follows. That is, the impurity concentration of the active layer 3 is controlled such that a depletion layer which can extend from the gate electrode 7 has a thickness larger than a thickness t.sub.1 of the active layer 3, and the entire region of the active layer 3 is depleted in an ON state of the SOI semiconductor element to realize the following effects:
(1) Suppression of mobility deterioration of carriers at an inverted surface immediately under the gate insulator is achieved by a decrease in effective electric field strength in the active layer, and a drain current is increased by this suppression. PA1 (2) A drain current is increased by an increase in carriers at the inverted surface in correspondence with a decrease in charge amount of the depletion layer in the active layer.
In an SOI semiconductor element with the above arrangement, since the active layer 3 is depleted by a gate-induced electric field, a drain-induced electric field applied from a drain junction to the active layer can be suppressed, and a short-channel effect of a threshold voltage can be suppressed. In addition, when a thickness t.sub.3 of the buried oxide film 2 immediately under the drain region 6 is increased, a parasitic capacitance can be decreased. Therefore, in the SOI semiconductor element of this type, the high-density integration and high-speed operation of the SOI semiconductor element are expected by down-scaling. In recent years, the SOI semiconductor element has received a great deal of attention for future applications.
However, when a thickness t.sub.2 of the buried oxide film 2 immediately under the active layer 3 is increased, it is apparent that the following drawback is posed. That is, the drain-induced electric field adversely affects an electric field distribution in the active layer 3 through the buried oxide film 2, thereby enhancing a short-channel effect.
In order to solve the drawback, when a thickness t.sub.4 of an oxide film 2 immediately under an active layer 3 is smaller than that in FIG. 2, as shown in FIG. 3, a thickness t.sub.5 of a buried oxide film in a drain region 6 is decreased. In this case, although the short-channel effect can be suppressed, a parasitic capacitance is increased due to a decrease in the thickness t.sub.5 of the buried oxide film 2 immediately under the drain region 6, thereby failing to achieve the high-speed operation of the SOI semiconductor element.
In contrast to this, an SOI semiconductor element shown in FIG. 4 is proposed to solve the above problems of the SOI semiconductor element shown in FIGS. 2 and 3. The same reference numerals as in FIG. 2 denote the same parts or parts having the same functions in FIG. 4. In FIG. 4, according to the characteristic features of the SOI semiconductor element, a buried electrode 7A is formed in a buried oxide film 2 for electrically insulating a p-type active layer 3 from a semiconductor substrate 1, and the buried electrode 7A is arranged immediately under the active layer 3 at a depth corresponding to a thickness t.sub.6.
With the above arrangement, a thickness t.sub.7 of the buried oxide film 2 immediately under a drain region 6 can be increased, and the thickness t.sub.6 of the buried oxide film 2 immediately under the active layer 3 can be decreased. Therefore, a decrease in parasitic capacitance of the drain region 6 and suppression of a short-channel effect can be realized, and the high-speed operation and down-scaling of the SOI semiconductor element can be achieved at the same time.
FIGS. 5A to 5E are views showing the steps of a method of manufacturing the conventional SOI semiconductor element shown in FIG. 4. This was reported at the International Electron Devices Meeting held by the IEEE (Institute of Electrical and Electronics Engineers) in 1990 (J. P. Colinge, M. H. Gao, A. Romano-Rodriguez, and C. Claes, "Silicon-On-Insulator Gate-All-Around Device". pp. 595-598).
As shown in FIG. 5A, a silicon oxide film 12A is buried in, e.g., a silicon semiconductor substrate to obtain a silicon semiconductor substrate S having a silicon substrate 11 and a first silicon semiconductor layer 11A.
As shown in FIG. 5B, the first silicon semiconductor layer 11A is processed by an anisotropic plasma etching technique or the like to have predetermined dimensions so as to form a silicon semiconductor layer 11a.
As shown in FIG. 5C, a photoresist is coated on the major surface of the semiconductor substrate, and the photoresist is exposed and developed to expose an oxide film 3a located at the underlying portion of the opposite end portions of the semiconductor layer 11a. Thereafter, an exposed oxide film 12 is etched by, e.g., hydrofluoric acid, and side etching caused by the etching removes the buried oxide film immediately under the silicon semiconductor layer 11a, thereby forming a hollow groove 12c under the semiconductor layer 11a. Note that reference numeral 13a in FIG. 5C denotes a buried oxide film after this groove is formed.
As shown in FIG. 5D, the major surface of the silicon substrate is exposed to an oxygenous ambiance to oxidize the surface of the silicon semiconductor layer 11a, thereby forming oxide films 13a, 13b, 13c and 13d. Thereafter, a silicon semiconductor layer 7X used as a gate electrode is deposited on the major surface of the silicon semiconductor substrate 11 by a technique such as a CVD method (Chemical Vapor Deposition method). At this time, by using the CVD method, a silicon semiconductor layer 7A can also be buried in the groove 12c.
Finally, as shown in FIG. 5E, the silicon semiconductor layer 7X on the semiconductor substrate is processed to have predetermined dimensions so as to form a gate electrode 7. Subsequently, n-type source and drain regions 5 and 6 are formed by, e.g., an ion-implantation technique or the like. Thereafter, when electrodes are formed, the SOI semiconductor element shown in FIG. 4 can be obtained. Note that reference numeral 3 in FIG. 5E denote a p-type active layer between the source region 5 and the drain region 6.
In the above manufacturing method, however, not only a removal width h of the buried oxide film 12 cannot be directly controlled as shown in FIG. 5C, but the dimensions of the oxide film 12 cannot be easily reproduced. On the other hand, as shown in FIG. 5E, the gate electrode in the buried oxide film 12, i.e., the buried electrode 7A, overlaps the source region 5 and the drain region 6 by lengths 1D and 1S, respectively. It is known that the parasitic capacitance of the SOI semiconductor element is increased in proportion to the lengths 1D and 1S to fail to achieve the high-speed operation of the SOI semiconductor element. In the above manufacturing method, the increase in parasitic capacitance of the overlap portion becomes a decisive drawback as the gate length is decreased.
In the above manufacturing method, since a part of the buried oxide film is removed to form a hollow portion, the thickness of the oxide film 13d is equal to that of the gate oxide film 13c. Therefore, a parasitic capacitance between the gate electrode 7 and the semiconductor substrate 11 is considerably increased, thereby failing to achieve the high-speed operation of the SOI semiconductor element.
As described above, although an SOI semiconductor element of this type has several advantageous characteristics, at the same time, it has the above problems. Therefore, the SOI semiconductor element is not practically used.
FIGS. 6A to 6H are views showing the steps of another method of manufacturing the semiconductor element using the buried electrode shown in FIG. 4. This example is disclosed in Japanese Patent Laid-Open No. 2-162740. In this example, a silicon oxide film 112 is formed on a silicon semiconductor substrate 111, and a polysilicon film 117 and a silicon oxide film 118 are sequentially formed in this order.
As shown in FIGS. 6B to 6F, the silicon oxide film 118, the polysilicon film 117, a silicon oxide film 16, a monocrystalline silicon film 115, a silicon oxide film 114, and a polysilicon film 113 are sequentially etched to expose the silicon oxide film 112. During this etching step, a floating gate electrode 117' is formed. Reference numeral 120 denotes a silicon nitride film; 119, a silicon oxide film; and 113', a backgate electrode.
Thereafter, as shown in FIG. 6G, silicon is epitaxially grown from the side surfaces of a channel portion 115', to form films 122a and 122b used as the source and drain regions. Note that reference numeral 123 denotes an oxide film; 124, a BSG or BPSG film; and 125a and 125b, aluminum interconnections.
However, in this manufacturing method, the following problems are posed.
First, since the silicon film 113' used as the second gate electrode is close to the films 122a and 122b used as the source and drain regions through a thin insulator 121 in a wide area, a gate-source parasitic capacitance and a gate-drain parasitic capacitance are considerably increased. According to this method, a gate capacitance is almost equal to these parasitic capacitances, thereby failing to achieve the high-speed operation of the semiconductor element.
Second, in this method, since the active region 115, is crystallized into a monocrystalline region such that amorphous silicon is melted by the radiation of a laser beam, the carrier mobility in this region is decreased to about 1/3 that of the monocrystalline silicon, a high-speed operation cannot be realized.
Third, in recent years, as the scale of an integrated circuit is increased, a multi-layered interconnection for connecting semiconductor devices to each other is demanded. At this time, in order to form the interconnection with a high yield, an underlying layer must be flattened. Therefore, recess and projecting portions of the underlying layer must be decreased before the interconnection step is started. In this condition, the structure described above goes against the current trend in semiconductor fabrication techniques, and it is understood that the structure cannot be easily applied to an integrated circuit in the future.